1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a dynamic random access memory (dynamic RAM) device having memory cells each comprising a single transistor and a single capacitor.
2. Description of the Related Art
As the memory capacity of semiconductor memory devices increases, an internal step-down circuit or the like is required to generate a voltage lower than the source voltage supplied from outside to operate the internal circuits of the devices. When they are operated with a lowered voltage of this sort, for example, in dynamic RAMs having memory cells each comprising a single transistor and a single capacitor, the charge storage of the memory cells become small, and the operation margin of the memory cells for sense amplification is also reduced. In order to prevent the above reduction of the operation margin, two methods have been taken to secure the signal level to be input into a sense amplifier. One of the methods is to increase the electric capacity of a capacitor of each memory cell, and the other is to reduce capacitance of the bit line which connects the memory cell and the sense amplifier.
However, with the method for providing the memory cell with a large capacitance, it becomes necessary to form a capacitance with a predesignated capacity within the memory cell which tends to become relatively smaller while meeting further increasing memory capacity of the semiconductor memory device, thereby requiring a thinner insulation film of the capacitor which also involves the expected risk of coming close to the physical limit. On the other hand, in order to reduce the capacitance of the bit line according to the other method, for example, the length of the bit line can be reduced by decreasing the number of memory cells to be connected to a bit line pair; however, this method increases the number of sense amplifiers and concomitantly increases the number of precharge circuits and transfer gates for data transfer, so that it is not suitable for use in high integration of the memory cell. Therefore, conventional dynamic RAMs have the drawback that it is difficult to prevent reduction of the operation margin of the sense amplifiers when they are operated with a lowered voltage.